[2025]


  • Jae-Geun Lim, Jun-Ho Boo, Hyoung-jung Kim, Jae-Hyuk Lee, Kang-Il Cho, and Gil-Cho Ahn, "A Two-Step ADC With a Separate DAC Method for Enhanced Sub-Quantizer Settling Condition," International Conference on Electronics, Information, and Communication, Feb. 2025.


[2024]


  • Kang-Il Cho, Jun-Ho Boo, Jae-Geun Lim, and Gil-Cho Ahn, "A CMOS Analog Front-End for Hall Sensor Readout IC," International Conference on Electronics, Information, and Communication, Feb. 2024.


[2023]


  • Seong-Bo Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Won-Jun Cho, and Gil-Cho Ahn, "A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer," International SoC Design Conference, Oct. 2023.


  • Mi-Ji Go, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Byeong-Ho Yu, Won-Jun Cho, Gil-Cho Ahn, "A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC," International SoC Design Conference, Oct. 2023.


[2022]


  • Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho Boo, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung-Hwan Choi and Gil-Cho Ahn, “A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor," International SoC Design Conference, Oct. 2022.


[2021]


  • Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, and Gil-Cho Ahn, "A 0.9V 0.022mm² 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique," IEEE Asian Solid-State Circuits Conference, Nov. 2021.


[2020]


  • Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim,  Jae-Geun Lim, Yong-Sik Kwak,  Seung-Hoon Lee, and Gil-Cho Ahn, “A Single-Trim Switched Capacitor CMOS Bandgap Reference with a 3σ Inaccuracy of +0.02%, 0.12% for Battery Monitoring Applications," IEEE Symposium on VLSI Circuits, pp. 1-2, Jun. 2020.


  • Tae-Gwan Kim, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak and Gil-Cho Ahn, "A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique," International SoC Design Conference, pp. 3-4, Oct. 2020.


  • Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak,  Jun-Sang Park, Seung-Hoon Lee, and Gil-Cho Ahn, “A 10-b 900-MS/s Single Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling," IEEE Asian Solid-State Circuits Conference, Nov. 2020. 


  • Jun-Sang Park, Je-Min Jeon, Jun-Ho Boo, Jae-Hyuk Lee, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, and Seung-Hoon Lee, “A 2.2mW 12-bit 200MS/s 28nm CMOS Piplined SAR ADC with Dynamic Register-Based High-Speed SAR Logic," IEEE Asian Solid-State Circuits Conference, Nov. 2020.


[2019]


  • Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Jun-Ho Boo, Seung-Hoon Lee, Gil-Cho Ahn, “A 10-b 320MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator,” IEEE Custom Integrated Circuits Conference, pp. 1-4, Apr. 2019.

 

  • Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, and Gil-Cho Ahn, “A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application," International SoC Design Conference, pp. 7-8, Oct. 2019.

[2018]

  • Ho-Jin Kim, Yong-Sik Kwak, Kang-Il Cho, Seung-Hoon Lee, Gil-Cho Ahn, “An analog front-end for self-capacitance touch sensing with environmental noise reduction technique,” International Conference on Electronics, Information, and Communication, pp. 1-3, Jan. 2018.


[2017]

  • Bum-Sik Chung, Hyeong-Kyu Kim, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, “Analog front-end for EMG acquisition system,” International SoC Design Conference, pp. 57-58, Nov. 2017

  • Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn, “A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators,” IEEE Asian Solid-State Circuits Conference, pp. 289-292, Nov.2017

[2015]

  • Dong-Joon Kim, Young-Ouk Kim, Gil-Cho Ahn, “A 12-bit 40-kS/s VCM-based switching C-C SAR ADC,” International SoC Design Conference, pp. 83-84. Nov. 2015.


[2014]


  • Mi-rim Kim, Young-Ouk Kim, Yong-Sik Kwak, Gil-Cho Ahn, “A 12-bit 200-kS/s SAR ADC with hybrid RC DAC,” IEEE Asia Pacific Conference on Circuits and Systems, pp. 185-188, Nov. 2014.

 

  • Joo-Won Oh, Yong-Sik Kwak, Gil-Cho Ahn, “A 10-bit 20-MS/s dual-channel algorithmic ADC with improved clocking scheme,” International SoC Design Conference, pp.56-57, Nov. 2014.


[2013]


  • Tai-Ji An, Jun-Sang Park, Yong-Min Kim, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee, “10b 150MS/s 0.4mm245nm CMOS ADC based on process-insensitive amplifiers,” IEEE International Symposium on Circuits and Systems, pp. 316-364, May. 2013.

 

  • Jun-Sang Park, Tai-Ji An, Yong-Min Kim, Suk-Hee Cho, Hyun-Sun Shim, Woo-Jin Jang, Yong-Jin Shin, Jun-Hyup Lee, Gil-Cho Ahn, Seung-Hoon Lee, “A 10b 50MS/s 90nm CMOS skinny-shape ADC using variable references for CIS applications,” International SoC Design Conference, pp.080-082, Nov. 2013.

[2012]


  • Young-Min Park, et.al., “A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer,” IEEE International Conference on Electronics, Circuits, and Systems, pp. 637-640, Dec. 2012.

 

  • Yong-Sik Kwak, Kwangsoo Kim, Gil-Cho Ahn, “A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference,” IEEE International Symposium on Circuits and Systems, pp. 520-523, May. 2012.

 

  • Jae-Hyeon Shin, Kang-Il Cho, Gil-Cho Ahn, “A digitally enhanced low-distortion delta-sigma modulator for wideband application,” International SoC Design Conference, pp. 108-111, Nov. 2012.

[2011]


  • J. Kim, T. Kwon, G. Ahn, Y. Kim, J. Kwon, "A ΔΣ ADC using 4-bit SAR type quantizer for audio applications ," International SoC Design Conference, pp. 73-75, Nov. 2011. 


  • C. Shin, M. Yoon, K. Cho, Y. Kim, K. Kim, S. Lee, G. Ahn, "A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC," IEEE International Symposium on Circuits and Systems, pp.1117-1120, May. 2011.


[2010]


  • S. Yoo, G. Noh, K. Kim, G. Ahn J. Lee, J. Lee, I. Choi, “A 1.6V ΣΔ ADC for digital electret microphone,”International SoC Design Conference, pp. 283-286, Nov. 2010.


  • X. Jiang, J. Song, T. Brooks, J. Chen, V. Chandrasekar, F. Cheung, S. Galal, D. Cheung,  G. Ahn, and M. Bonu, “A 10mW stereo audio CODEC in 0.13 um CMOS,” IEEE Int. Solid-State Circuits Conf., pp. 82-83, Feb. 2010.


[2009] 


  • B. Park, S. Ji, M. Choi, K. Lee, G. Ahn, and S. Lee, “A 10b 100MS/s 25.2mW 0.18 um CMOS ADC with various circuit sharing techniques,” International SoC Design Conference, pp. 329-332, Nov. 2009.


  • Y. Kim, H. Choi, K. Lee, G. Ahn, S. Lee, J. Kim, K. Moon, M. Choi, K. Moon, H. Park, and B. Park, “A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers,” IEEE Custom Int. Circuits Conf., pp. 271-274, Sep. 2009.


[2008]


  • M. Kim, V. Kratyuk, P. Hanumolu, G. Ahn, S. Kwon, and U. Moon, “An 8mW 10b 50MS/s pipelined ADC using 25dB opamp, ” IEEE Asian Solid-State Circuits Conf., pp. 49-52, Nov. 2008.


[2007]


  • J. Carnes, G. Ahn, and U. Moon, “A 1V 10b 60MS/s hybrid opamp-reset/switched-RC pipelined ADC,”IEEE Asian Solid-State Circuits Conf., pp. 236-239, Nov. 2007.


  • G. Ahn, M. Kim, P. Hanumolu, and U. Moon, “A 1V 10b 30MSPS switched-RC pipelined ADC,” IEEE Custom Int. Circuits Conf., pp. 325-328, Sep. 2007.


[2006]


  • M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, “A 0.9V 92dB double-sampled switched-RC delta-sigma audio ADC,” Dig. Symp. VLSI Circuits, pp. 200-201, Jun. 2006.


  • G. Ahn, et.al., “A 12b 10MS/s pipelined ADC using reference scaling,” Dig. Symp. VLSI Circuits, pp. 272-273, Jun. 2006.

 

[2005]


  • G. Ahn et.al., “A 0.6V 82dB delta-sigma audio ADC using switched-RC integrators,” IEEE Int. Solid-State Circuits Conf., pp. 166-167, Feb. 2005.

[2004]


  • J. Li, G. Ahn, D. Chang and U. Moon, “0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR,” Dig. Symp. VLSI Circuits, pp. 436 - 439, Jun. 2004.

 

  • M. Kim, G. Ahn and U. Moon, “An improved algorithmic ADC clocking scheme,” IEEE Int. Symp. Circuits Syst., vol. 1, pp. 589 - 592, May 2004.

[2003]


  • D. Chang, G. Ahn, and U. Moon, “A 0.9V 9mW 1MSPS digitally calibrated ADC with 75dB SFDR,” Dig. Symp. VLSI Circuits, pp. 67 - 70, Jun. 2003.