[2025]

  • Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Seong-Bo Park, Seung-Hun Park, Myoungbo Kwak, Jaewoo Park, Young Choi, Jun-Ho Boo,  Gil-Cho Ahn, "A 7-Bit 700 MS/s 2b/Cycle Asynchronous SAR ADC WithPartially Merged Capacitor Switching," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 61, no. 1, Aug. 2025.

  • Tae-June Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Won-Jun Cho, Gil-Cho Ahn, "A BJT-based CMOS Temperature Sensor With a ±0.94℃ 3σ-inaccuracy From -40℃ to +150℃," Journal of Semiconductor Technology and Science, vol. 25, No. 3, pp. 236-244, June. 2025.

  • Seung-Hun Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Seong-U Choi, Gil-Cho Ahn, "A 232.2nW Segmented Curvature Sub-BGR with Bandgap Core Reusing," Journal of Semiconductor Technology and Science, vol. 25, No. 3, pp. 267-273, June. 2025.


  • Jae-Geun Lim, Jun-Ho Boo, Jae-Hyuk Lee, Hyoung-Jung Kim, Byeongho Yu, Kang-il Cho, Sungho Lee, Un-Ku Moon, Gil-Cho Ahn, "A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues," IEEE Journal of Solid-State Circuits, pp. 1-12, June. 2025. (Early Access)


  • Ji-Ho Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Joo-Yeul Yang, Gil-Cho Ahn, "A Second-Order Delta-Sigma Modulator for Battery Management System DC Measurement," Journal of Semiconductor Technology and Science, vol. 25, No. 1, pp. 14-20, Feb. 2025.


[2023]

  • Byeong-Ho Yu, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Gil-Cho Ahn, "A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2nd Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control," Journal of Semiconductor Technology and Science, vol. 23, No. 5, pp. 265-272, Oct. 2023.


  • Jae-Hyuk Lee, Jun-Ho Boo, Jun-Sang Park, Tai-Ji An, Hee-Wook Shin, Young-Jae Cho, Michael Choi, Jin-Wook Burm, Gil-Cho Ahn, Seung-Hoon Lee, "11 b 200 MS/s 28-nm CMOS 2b/cycle successive-approximation register analogue-to-digital converter using offset-mismatch calibrated comparators," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 59, no. 16, Aug. 2023.

  • Ho-Jin Kim, Jun-Ho Boo, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn, "A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 2, pp. 401-405, Feb. 2023.


  • Jae-Hyuk Lee, Jun-Ho Boo, Jun-Sang Park, Tai-Ji An, Hee-Wook Shin, Young-Jae Cho, Michael Choi, Jin-Wook Burm, Gil-Cho Ahn, and Seung-Hoon Lee, “A 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme," Journal of Semiconductor Technology and Science, vol. 23, No. 2, pp. 118-127, Apr. 2023.


[2021]

  • Ho-Jin Kim, Jun-Ho Boo, Jae-Hyuk Lee, Jun-Sang Park, Tai-Ji An, Sung-Han Do, Young-Jae Cho, Michael Choi, Gil-Cho Ahn, and Seung-Hoon Lee, "A 70 dB SNDR 10 MS/s 28 nm CMOS Nyquist SAR ADC with Capacitor Mismatch Calibration Reusing Segmented Reference Voltages," Journal of Semiconductor Technology and Science, vol. 21, no. 6, pp. 449-458, Dec. 2021.


  • Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, and Gil-Cho Ahn, “A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications," IEEE Journal of Solid-State Circuits, vol. 56, issue. 4, pp. 1197-1206, Apr. 2021.


  • Ju-Hye Han, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Jae-Sang Kim, and Gil-Cho Ahn, "A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback", IEEE Transactions on Circuits and Systems II, vol. 68, issue. 5, pp. 1645-1649, 17 Mar. 2021.

  • Jae-Geun Lim, Je-Min Jeon, Jun-Ho Boo, Yoon-Bin Im, Jae-Hyuk Lee, Sung-Han Do, Young-Jae Cho, Michael Choi, Gil-Cho Ahn, and Seung-Hoon Lee, “A Non-binary C-R Hybrid DAC for 12 b 100 MS/s CMOS SAR ADCs with Fast Residue Settling," Journal of Semiconductor Technology and Science, vol. 21, No. 4, pp. 255-261, Aug. 2021.


[2020]

  • Jun-Sang Park, Tai-Ji An, Hee-Cheol Choi, Gil-Cho Ahn, and Seung-Hoon Lee, "A 12-bit 180 MS/s Current-Steering DAC with Cascaded Local-element Matching Topologies," Journal of Semiconductor Technology and Science, vol. 20, no. 1, pp. 99-104, Feb. 2020.

  • Jun-Sang Park, Dong-Hyun Kim, Tai-Ji An, Min-Kyu Kim, Gil-Cho Ahn, and Seung-Hoon Lee, "12 b 50 MS/s  0.18 ㎛ CMOS SAR ADC based on highly linear C-R hybrid DAC," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 56, no. 3, pp. 119-121, Feb. 2020


[2019]

  • Jun-Sang Park, Tai-Ji An, Gil-Cho Ahn, Seung-Hoon Lee, “A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, issue. 7, pp. 1119-1123, Jul. 2019



[2018]

  • Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn, “A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta–Sigma Modulator Using Source-Follower-Based Integrators,” IEEE Journal of Solid-State Circuits, vol. 53, issue. 10, pp. 2772-2782, Oct. 2018.

 

  • Yong-Sik Kwak, Min-Ho Yun, Seung-Hoon Lee, and Gil-Cho Ahn, “A 1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique,” Journal of Semiconductor Technology and Science, vol. 18, no. 3, pp. 346-351, Jun. 2018.

 

  • Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Gil-Cho Ahn, “A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture,” IEICE Electronics Express, vol. 15, no. 21, pp. 20180848-20180848, Sep. 2018.

 

  • Tai-Ji An, Moon-Sang Hwang, Won-Jun Choe, Gil-Cho Ahn, Seung-Hoon Lee, “Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC’s”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, issue. 10, pp.3227-3240, Oct. 2018.

 

  • Hyeong-Kyu Kim, Bum-Sik Chung, Kang-Il Cho, Ho-Jin Kim, and Gil-Cho Ahn, “Analog Front-end for EMG Acquisition System,” Journal of Semiconductor Technology and Science, vol. 18, no. 6, pp. 667-676, Dec. 2018.

[2017]

  • Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, “A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique,” IEICE Electronics Express, vol. 14, issue. 21, p. 20171007, Nov. 2017.

  • Tai-ji An, Young-Sea Cho, Jun-Sang Park, Gil-Cho Ahn, and Seung-Hoon Lee, “A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch,” Journal of Semiconductor Technology and Science, vol. 17 no. 5 pp. 636-640, Oct. 2017.

  • Min-Sik Kim, Kang-Il Cho, Yong-Sik Kwak, Sangwon Lee, Jaewoo Choi, and Gil-Cho Ahn, “A 19.5 ps-LSB Vernier-type Time-to-digital Converter for PET,” Journal of Semiconductor Technology and Science, vol. 17, no. 6, pp. 800-805, Dec. 2017.

[2016]

  • Jun-Sang Park, Jong-Min Jeong, Tai-Ji An, Gil-Cho Ahn, and Seung-Hoon Lee, “Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors,” Journal of Semiconductor Technology and Science, vol. 16, no. 1, pp.70-79 Feb. 2016.

  • Park, Jun-Sang, An, Tai-Ji, Ahn, Gil-Cho, Lee, Mun-Kyo, Go, Min-Ho, Lee, Seung-Hoon, “A 13b 100MS/s 0.70㎟ 45nm CMOS ADC for IF-Domain Signal Processing Systems,” Journal of the Institute of Electronics and Information Engineers, vol. 53, issue. 3, pp. 46-55. May. 2016.

  • Tai-Ji An, Gil-Cho Ahn, Seung-Hoon Lee, “High-efficiency low-noise pulse-width modulation DC–DC buck converter based on multi-partition switching for mobile system-on-a-chip applications,” IET Power Electronics, vol. 9, Issue. 3, pp. 559-567, Mar. 2016. 

[2014]

  • Won-Tak Choi, Gil-Cho Ahn, “A 1.1 V 81.8 dB Delta-Sigma ADC,” International Journal of Control and Automation, vol. 7, no. 3, pp.219-224, Sep. 2014.

  • Seung Yong Bae, Jong Do Lee, Eun Ju Choe, Gil Cho Ahn, “Low Distortion Analog Front-End for Digital Electret Microphone,” Applied Mechanics and Materials, vols. 475-476, pp. 1633-1637, 2014.

  • Jun-Sang Park, Tai-Ji An, Suk-Hee Cho, Yong-Min Kim, Gil-Cho Ahn, Ji-Hyun Roh, Mun-Kyo Lee, Sun-Phil Nah, and Seung-Hoon Lee, “A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs,“ Journal of Semiconductor Technology and Science, vol.14, no.2, pp. 184-189, Apr. 2014.

  • Suk-Hee Cho, Jun-Sang Park, Gil-Cho Ahn, Seung-Hoon Lee, “A 14–10 b dual-mode low-noise pipeline ADC for high-end CMOS image sensors,” Analog Integrated Circuits and Signal Processing, vol. 80, issue. 3, pp. 437-447, Sep. 2014.

  • Jong Do Lee, Jae Hyeon Shin, Young Min Park, Yong Sik Kwak, Gil Cho Ahn, “A 2nd Order Delta-Sigma ADC for Pressure Sensor Interface,” Applied Mechanics and Materials, vols. 475-476, pp. 554-559, 2014.

[2013]

  • Eun-Ju Choe, Seok Heo, Yong-Sik Kwak, Gil-Cho Ahn, “A 10-bit 2MS/s SAR ADC Using a Dynamic Element Matching Technique,” International Journal of Emerging Technology and Advanced Engineering, vol. 3, issue. 12, pp. 70-74, Dec. 2013.

[2011]

  • Byeong-Woo Koo, Seung-Jae Park, Gil-Cho Ahn, Seung-Hoon Lee, “A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques,” IEICE Transactions on Electronics, Vol. E94-C, No. 8 pp.1282-1288 , Aug. 2011.

  • C. Shin and G. Ahn, "A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique,"  Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.58, pp.274-278, May 2011.

  • H. Choi, P. Yoo, G. Ahn and S. Lee, “A 14b 150 MS/s 140 mW 2.0mm2 0.13 um CMOS A/D converter for software-defined radio systems,” International Journal of Circuit Theory and Applications, vol. 39, pp.135-147, Feb. 2011.

[2010]

  • Y. Kim, H. Choi, G. Ahn, and S. Lee, “A 12 bit 50 MS/s CMOS Nyquist A/D converter with a fully differential class-AB switched op-amp,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 620-628, Mar. 2010.

  • G. Noh and G. Ahn, "A 2.5V 109 dB  DR ΔΣADC for Audio Application,"  Journal of Semiconductor Technology and Science, vol. 10, pp.276-281, Oct. 2010.


  • M. Choi, G. Ahn and S. Lee, “12b 50 MS/s 0.18 um CMOS ADC with highly linear input variable gain amplifier,” Electron Lett., vol. 46, no. 18, pp. 1254-1256, Sep. 2010.


[2009]


  • H. Choi, Y. Kim, G. Ahn, and S. Lee, “A 1.2-V 12-b 120-MS/s SHA-free dual-channel Nyquist ADC based on midcode calibration,” IEEE Trans. Circuits Syst. I, vol. 56, no. 5, pp. 894 - 901, May. 2009.


[2008]


  • M. Kim, G. Ahn, P. Hanumolu, S. Lee, S. Kim, S. You, J. Kim, G. Temes, and U. Moon, “A 0.9V 92dB double-sampled switched-RC delta-sigma audio ADC,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1195-1206, May 2008.


[2005]


  • G. Ahn et.al., “A 0.6V 82dB delta-sigma audio ADC using switched-RC integrators,” IEEE J. Solid-State Circuits, pp. 2398-2407, Dec. 2005.


  • J. Li, G. Ahn, D. Chang, and U. Moon, “A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR,” IEEE J. Solid-State Circuits, pp. 960-969, Apr. 2005.


  • D. Chang, G. Ahn and U. Moon, “Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters,” IEEE Trans. Circuits Syst. I, vol. 52, pp. 1 - 12, Jan. 2005.